1. Technical Field
The present disclosure relates generally to audio power amplifiers, and more particularly to class D amplifiers.
2. Description of the Related Art
Class D audio power amplifiers are developing rapidly in various applications such as MP3, mobile phone, home theater and so on. They have become the preferred solution in audio systems.
Output power transistors of class D amplifiers work in switch states, their theoretical efficiencies can reach 100%, and their actual efficiencies may be over 90%, compared to actual efficiencies of conventional amplifiers are about 60% or less. The improvement of efficiency may take two advantages: low power consumption and low heat generation. Low heat generation can greatly decrease the size of the heat sink and the area of the PCB of a chip having the class D amplifier. Therefore, the class D amplifier becomes more and more attractive to portable electronics and consumer electronics.
The common modulation principle for a modern class D audio power amplifier is the Pulse Width Modulation (PWM). FIG. 1 is a schematic diagram of a half-bridge class D amplifier incorporating the pulse width modulation. Referring to FIG. 1, the half-bridge class D amplifier includes a pre-operational amplifier, a PWM comparator, a logic circuit, an output power transistor including two MOSFETs, and an external low-pass filter (formed by inductor L and capacitor C) used for restoring amplified audio signal.
The process of the pulse width modulation includes: an audio input signal Vi is amplified by the pre-operational amplifier then to be output as an amplified audio signal Vsin; the amplified audio signal Vsin, is modulated to a pulse signal Vp via a high frequency triangle signal Vosc of the PWM comparator, the pulse signal Vp is as a PWM signal; the PWM signal Vp passes through the logic circuit and drives the output power transistor to output a switch signal Vm; and the switch signal Vm is restored to an audio signal Vout by the LC low-pass filter.
An ideal input-output waveform of the PWM comparator is shown in FIG. 2. According to FIG. 2, when Vsin is higher than Vosc, the PWM signal Vp is output at a high level; when Vsin is lower than Vosc, Vp is output at a low level. This modulation mode is generally called “natural sampling”, in which a frequency fosc of the high frequency triangle signal Vosc is designated as a sampling frequency. In practice, for a balance of efficiency and cost, fosc may be set at about 250 kHz. If fosc is lower than 250 kHz, the efficiency of the class D amplifier may be higher, but a much larger external filter is needed. While fosc is higher than 250 kHz, the situation may be the reverse. The frequency fosc of the high frequency triangle signal Vosc is much higher than that of the audio signal Vsin (20 Hz˜20 kHz), the pulse width (duty cycle) of the PWM signal Vp in each cycle time of the triangle signal is directly proportional to the amplitude of the amplified audio signal Vsin, which means an audio signal is transformed to pulse signals with different pulse widths.
According to the above description, the PWM comparator is a crucial module in the generation of the PWM signal. According to practical dealt with audio signals, PWM comparators shall have: (1) large bandwidths for achieving high conversion speed; (2) high-gains for achieving high-precision; (3) great noise resistance abilities to ensure that the PWM signal Vp can flip correctly in noisy environment. According to FIG. 2, in a correct modulation process, the PWM signal Vp can only flip from high level to low level on a rising edge of the triangle signal, while the PWM signal Vp can only flip from low level to high level on a falling edge of the triangle signal.
According to FIG. 3, a conventional PWM comparator includes: a pre-amplify circuit, a judge circuit, and an output s circuit. Referring to the judge circuit, a gate of an NMOSFET M6 is connected with a drain of an NMOSFET M7, a gate of the NMOSFET M7 is connected with a drain of the NMOSFET M6, such that a positive feedback is obtained, and the gain of the judge circuit is increased. Further, the connection may achieve to suppress noises by producing a hysteresis. Given that a transconductance gm1 of an NMOSFET M1 for receiving Vsin and a transconductance gm2 of an NMOSFET M2 for receiving Vosc are respectively equal to gm, a width to length ratio (W/L)6,7 of the NMOSFETs M6 and M7 is βB, a width to length ratio of NMOSFETs M5 to M8 (W/L)5,8 is βA, and βB≧βA. In steady states, NMOSFETs M6 and M7 work only in cutoff region or linear region. Given that a drain current ID3 of a PMOSFET M3 is equal to Iss, and a drain current ID4 of a PMOSFET M4 is equal to 0, NMOSFETs M5 and M7 would be active, and NMOSFETs M6 and M8 would be cutoff. With a gradual increase of ID4, ID3 would gradually decrease, and an electric potential of the NMOSFET M7 would increase until the NMOSFET M7 goes into saturation region. At the point that equation (1) below is established:
                              I                      D            ⁢                                                  ⁢            4                          =                                                            β                B                            2                        ⁢                                          (                                                      V                    A                                    -                                      V                    THN                                                  )                            2                                =                                                    β                B                                            β                A                                      ⁢                          I                              D                ⁢                                                                  ⁢                3                                                                        (        1        )            the threshold point of the current ID4 would be the boundary that the PWM signal Vp flips from high level to low level. After the NMOSFET M7 goes into the saturation region, the NMOSFETs M5 and M7 are cutoff, the NMOSFETs M6 and M8 are active. Similarly, under the situation that ID3 increases and ID4 decreases, at the boundary that the equation (2) below is established, the PWM signal Vp would flip from low level to high level:
                              I                      D            ⁢                                                  ⁢            3                          =                                            β              B                                      β              A                                ⁢                      I                          D              ⁢                                                          ⁢              4                                                          (        2        )            According to equation (1) and equation (3) below:
                              I                      D            ⁢                                                  ⁢            3                          =                                                                              g                  m                                2                            ⁢                              (                                                      V                    sin                                    -                                      V                    osc                                                  )                                      +                                          I                ss                            2                                =                                    I              ss                        -                          I                              D                ⁢                                                                  ⁢                4                                                                        (        3        )            it could be concluded that:
                              V          SPH                =                                            V              sin                        -                          V              osc                                =                                                                      I                  ss                                                  g                  m                                            ⁢                                                                    β                    A                                    -                                      β                    B                                                                                        β                    A                                    +                                      β                    B                                                                        =                          -                              V                SPL                                                                        (        4        )            wherein VSPH is the flipping upper limit of the PWM comparator (flipping from low level to high level), VSPL is the flipping lower limit of the PWM comparator (flipping from high level to low level).
Referring to FIG. 4, a hysteresis transfer characteristic curve of the PWM signal Vp is shown. The abscissa thereof stands for the value of the difference of Vsin minus Vosc, the ordinate thereof expresses the value of Vp. The changes of the PWM signal Vp are:when Vsin−Vosc>VSPH, Vp=GND→VCC; when Vsin−Vosc<VSPL, Vp=VCC→GND  (5)VH=VSPH−VSPL  (6)
However, conventional PWM comparators have these disadvantages:
1) According to equations (4) and (5), once the size of the devices (width to length ratio) is determined, the flipping upper limit VSPH and the flipping lower limit VSPL are fixed, which means the hysteresis section VH is fixed. When PWM are used in audio applications, fixed VH would have disadvantages. When the amplitude of Vosc approaches to Vsin, due to the existence of noises, Vp is prone to flip incorrectly if the VH is set too small. It means that a big noise can make Vp to flip from low level to high level on rising edge of the triangle signal.
2) On the falling edge of the triangle signal Vosc, Vp may flip from high level to low level by mistake. This mistake may happen in the case that the duty cycle of a switch signal is nearly 100%. In that time the triangle signal is in the process of changing from the falling edge to the rising edge. Normally, the triangle signal is obtained through charging and discharging of a capacitor, which would be easy to generate a relatively large noise. If the hysteresis section VH is determined to be too large, the resolution of the PWM comparator will decrease significantly, which would cause a relatively large distortion.